1. Field of the Invention
The present invention relates to a floor plan editing apparatus for semiconductor integrated circuits.
2. Description of Related Art
In designing a layout of a semiconductor integrated circuit, a floor planning is performed. “Floor planning” refers to determination of a layout of main component parts, such as hierarchical modules, which are portions of a semiconductor integrated circuit, terminals of the hierarchical modules, hard macros and terminals of the hard macros dialogically, performed by a designer using a graphical interface (GUI) of a computer before determination of a layout of components (logic gate elements and sequential circuits) of the semiconductor integrated circuit. An apparatus for supporting such an operation may be referred to as a “floor plan editing apparatus”.
When a designer lays out a semiconductor integrated circuit by using the floor plan editing apparatus, floor planning of the semiconductor integrated circuit may be performed in the floor plan editing apparatus.
In the process of the floor planning, the shapes of hierarchical modules, a disposition of the hierarchical modules and positions of terminals are determined so as to avoid a state where the number of wiring lines between the hierarchical modules is so large that wiring with respect to the hierarchical modules in a wiring step performed after the floor planning becomes impossible, and a state where a wiring distance is so large that a delay time in transmission of signals becomes excessively long. Also, a disposition of hard macros, positions of terminals of the hierarchical module and distances between the hard macros may be determined so as to avoid a state where the terminal of one of the hierarchical modules or a terminal of one of the hard macros becomes so close to a terminal, which is connected with the terminal of the hierarchical modules or the terminal of the hard macros, that wiring process becomes impossible due to congestion of wiring, and a state where the wiring distance is so large that an unnecessary space may be made.
The floor plan editing apparatus enables the designer to easily recognize visually, for example, connection relationships, the number of wiring lines and the wiring distances between the hierarchical modules and the hard macros. The floor plan editing apparatus displays data which includes terminals and wirings (paths) between the terminals. The floor plan editing apparatus generates the data on the basis of circuit connection information (net nest) representing, for example, connection relationships, the number of wiring lines and a wiring distance between the terminals of the hierarchical modules, between terminals of the hierarchical modules and the hard macros and between the terminals of hard macros. Paths of the display data are displayed as line segments such as straight lines. Such display data is called a “rat's nest” or “fly-lines”. For example, display of the rat's nest is described in Non-Patent Document 1.
In many cases, the terminals of the semiconductor integrated circuit may be connected to each other via a plurality of logic gate elements and a plurality of sequential circuits disposed in paths, particularly in paths between the terminals of the hierarchical modules and the terminals of hard macros and between the terminals of hard macros.
In Patent Document 1, when one or more the logic gate elements or the sequential circuits are disposed in a path between two terminals, the rat's nest showing the two terminals, the path and the logic elements and the sequential circuits, is displayed.
A designer may consider a delay in transmission of signals between terminals via the path to examine suitable positions for arranging the hierarchical modules and the hard macros on a chip. For example, a designer may examine suitable positions at which the terminals of the hierarchical modules and the terminals of the hard macros are disposed on a chip after considering whether or not the delay between the terminals may be within one clock cycle. However, when the designer lays out a semiconductor integrated circuit by using the floor plan editing apparatus in the related art, the floor plan editing apparatus only displays the rat's nest. It is difficult to examine the suitable positions at which the terminals of the hierarchical modules and the terminals of the hard macros based on only the rat's nest. Therefore, there is a need for enabling examination of the suitable positions at which the terminals of the hierarchical modules and the hard macros are disposed on the chip.
Related arts will be described below.
Japanese Patent Laid-Open No. 2006-293701, as the above-mentioned Patent Document 1, discloses a net display program for displaying connections between components to be mounted on a substrate. With the net display program, the computer executes a process of recognizing a plurality of components designated in components displayed on a screen, another process of tracing, in a direction in which an electrical signal propagates or in a direction in which the electrical signal is propagated, a connection destination with respect to a signal line connected to a terminal of a first component which is optionally one of the designated components, and another process of connecting, by a connection line, the first component and a designated second component different from the first component if a terminal of the second component is included in the traced signal line, and displaying the connection line.
Japanese Patent Laid-Open No. 2006-301961 discloses an automatic floor planning method (Patent Document 2). According to the automatic floor planning method, in designing a hierarchical layout of a semiconductor integrated circuit constituted by one (or more) black box block having at least block boundary input and output information and having a shape and area set in advance, and one (or more) white box block having information on constituent elements in the block and connections of the constituent elements as well as block boundary input and output information, the shapes and areas of the blocks are determined on the basis of the results of flat disposition made by developing and disposing a hierarchical structure.
The automatic floor planning method includes making the flat disposition by setting a polygonal shape, a circular shape or an elliptic shape in the black box block as a core region of the black box block and by permitting, with respect to a region other than the core region, overlapping between the positions at which the internal constituent elements of the black box block and the hierarchy-developed white box block are disposed, checking an overlap between the positions at which the internal constituent elements of the black box block and the white box block are disposed, and changing the shape and area of the black box block according to the overlap, and sequentially repeating the above-mentioned steps until a set condition is satisfied.
Japanese Patent Laid-Open No. 11-213029 discloses a register transfer level logical description hardware performance evaluation apparatus (Patent Document 3). The register transfer level logical description hardware performance evaluation apparatus has a register transfer level logical description input thereto, and makes a predictive evaluation of LSI hardware performance. This apparatus is provided with block area estimation means for determining the size of each of the blocks and the relative positional relationships between the blocks on the basis of the logical description, path delay computation means for obtaining net delays on the basis of information on the relative positional relationships between the blocks by considering three-dimensional capacities, power consumption computation means for computing power consumption, and inter-system evaluation means for displaying tradeoffs in evaluation values by the above-described means with respect a plurality of register transfer level logical descriptions.
Japanese Patent Laid-Open No. 10-340291 discloses a method of making a logical simulation model (Patent Document 4). The method of making a logical simulation model includes logical combination means for extracting a logical block from verified logic circuit information and optimizing the logic of the logic block, and delay information preparation means for extracting timing information from the logic circuit information, and erasing redundant processing by determining at the time of preparing a model an element operation sequence on the basis of the connection relationships between combination circuits and sequential elements while considering an asynchronous loop, whereby high-speed simulation is made possible.
Japanese Patent Laid-Open No. 2003-223479 discloses a circuit designing apparatus (Patent Document 5). The circuit designing apparatus is provided with a logic designing unit which performs logic designing with respect to a circuit to be designed, a disposition unit which disposes cells on the basis of the results of logic designing performed by the logic designing unit, and a wiring unit which performs wiring between the cells disposed by the disposition unit. A path tracing unit performs path tracing from one or more tracing start pins with respect to the results of disposition by the disposition unit or the results of wiring by the wiring unit, and a delay value computation unit, when pass tracing is performed by the path tracing unit, computes the maximum or minimum of totalized delay values from the one or more tracing start pins to pins of the cells to be disposed, through which paths extend. A gate stage number computation unit, in a state where a unit delay value is assigned to all the cells to be designed and where 0 is assigned as a delay value to all nets between the cells, after logic designing by the logic designing unit, makes the delay value computation unit compute the maximum or minimum of the totalized delay values while path tracing is being performed by the path tracing unit with respect to the results of logic designing performed by the logic designing unit. The gate stage number computation unit also computes the numbers of gate stages between sequential circuit cells or between input and output pins and the sequential circuit cells in the circuit to be designed on the basis of the maximum or minimum of the total delay values.
Japanese Patent Laid-Open No. 2005-228124 discloses a method of generating hierarchical blocks in a semiconductor integrated circuit design (Patent Document 6). In the method of generating hierarchical blocks in a semiconductor integrated circuit design, a plurality of hierarchical blocks are generated using a computer from circuit information in which logical hierarchy information about a semiconductor integrated circuit is held. This hierarchical block generating method includes a circuit structure extraction step of inputting circuit information in which logical hierarchy information about the semiconductor integrated circuit is held, and extracting a circuit structure from the input circuit information with respect to logical hierarchical layers in the semiconductor integrated circuit. Also included is a hierarchical block generation step of generating a plurality of hierarchical blocks by combining the logical hierarchical layers on the basis of the circuit structure of the logical hierarchical layers and outputting the structure of the generated hierarchical blocks.    [Non-Patent Document 1] “Blast Plan Pro” published from Magma Design Automation, Co., Ltd., catalog page 2, [online], 2005, [by search on Jun. 25, 2007], Internet <URL:http://www.magma-da.co.jp/product/image_pr/PDF/PanPro200506.pdf>    [Patent Document 1] Japanese Patent Laid-Open No. 2006-293701    [Patent Document 2] Japanese Patent Laid-Open No. 2006-301961    [Patent Document 3] Japanese Patent Laid-Open No. 11-213029    [Patent Document 4] Japanese Patent Laid-Open No. 10-340291    [Patent Document 5] Japanese Patent Laid-Open No. 2003-223479    [Patent Document 6] Japanese Patent Laid-Open No. 2005-228124